1. Field of the Invention
The present invention relates to a method for manufacturing a hetero-junction field effect transistor (HFET) device, and more particularly, to a method for manufacturing an AlGaN/GaN HFET device, which is capable of forming a fine gate electrode pattern and elevating the degree, to which a gate electrode are aligned with ohmic electrodes.
2. Description of the Related Art
As a frequency band for wireless communication services increases, processes for manufacturing communication devices becomes more complicated and more difficult. In the manufacture of a hetero-structure field effect transistor device, which is used as an amplification device for high frequency communication, techniques of forming a source electrode, a drain electrode, and a gate electrode are very important to determine the electrical characteristics and frequency characteristics of the device.
An AlGaN/GaN HFET device is a device which is capable of maximizing mobility of electrons by forming a hetero junction of AlGaN having a large band gap and GaN having a narrow band gap together to form a quantum well at the interface therebetween and thus trapping the electrons in the quantum well. In the HFET device, the amount of current is controlled by applying voltage to a gate electrode in Schottky contact with the semiconductors, in which electrons flow along a channel between a source electrode and a drain electrode that are in ohmic contact with the semiconductors. Accordingly, the contact resistance of the ohmic electrodes (i.e., the source and drain electrodes) strongly affects the direct current characteristics of the HFET device, such as drain current, transconductance, or knee voltage, and the frequency characteristics of the HFET device, such as associate gain or power added efficiency. Until now, in order to improve the electrical characteristics and frequency characteristics of a HFET device, various efforts have been made to decrease the gap between source and drain electrodes and reduce the size of a gate electrode formed between ohmic electrodes to below a sub-micron level. Accordingly, techniques of manufacturing a fine gate electrode in a narrow gap between source and drain electrodes and aligning the gate electrode with the source and drain electrodes are very important to determine the reproducibility and performance of a HFET device.
FIGS. 1A through 1D are views illustrating a conventional method for manufacturing a HFET device. Referring to FIG. 1A, a non-doped GaN semiconductor layer (I-GaN semiconductor layer) and an AlGaN semiconductor layer are sequentially deposited on a sapphire substrate. Next, referring to FIG. 1B, devices are isolated by etching the substrate to a predetermined depth of the i-GaN semiconductor layer. Next, referring to FIG. 1C, a source electrode (S) and a drain electrode (D) are formed on the AlGaN semiconductor layer and are rapidly heat-treated at a temperature of no less than 600xc2x0 C. for 10 or more seconds, thereby forming an ohmic contact. Since the ohmic contact is formed at a high temperature of no less than 500xc2x0 C., an area of ohnimic electrode in the direction of the width of the AlGaN semiconductor is increased, and thus the gap between the source electrode (S) and the drain electrode (D) becomes narrower.
Next, referring to FIG. 1D, a gate electrode pattern is formed of photoresist. Next, a gate electrode (G) is formed using the gate electrode pattern.
However, the gate electrode (G) may lose its Schottky characteristics according to conditions of heat treatment. Thus, in the above method, the gate electrode (G) is formed after the source electrode (S) and the drain electrode (D) are deposited and heat-treated to form the ohmic electrodes.
In the meantime, as the line width of a gate electrode of a device becomes smaller, the characteristics of the gate electrode become superior. However, in the case of a photoresist layer pattern used to form a photoresist layer pattern used to form a fine gate electrode on a substrate having a step difference introduced by a source electrode and a drain electrode, the thickness of a photoresist layer is greatest between the source electrode and the drain electrode on the surface of the substrate. Thus, it becomes more difficult to form a fine gate electrode pattern, and the reproducibility of the formation of a gate electrode pattern may be lowered. Accordingly, it is difficult to form a gate electrode having a small line width and thus satisfy a design rule previously set when designing a semiconductor device.
To solve the above-described problems, it is an object of the present invention to provide a method for manufacturing an AlGaN/GaN HFET device, which is capable of easily forming a fine gate electrode pattern.
Accordingly, to achieve the above object, there is provided a method for manufacturing a hetero-junction field effect transistor (HFET) device. The method includes (a) sequentially forming a non-doped GaN semiconductor layer and an AlGaN semiconductor layer on a substrate, (b) separating devices from each other by etching the substrate, (c) forming a photoresist layer pattern on the AlGaN semiconductor layer and forming gate electrodes by depositing a material on the substrate using the photoresist layer pattern, (d) treating the surface of the AlGaN semiconductor layer, and (e) forming a photoresist layer pattern on the substrate and forming ohmic electrodes by depositing a metal on the substrate using the photoresist layer pattern.
The step (d) is preferably performed using inductively coupled plasma (ICP). The step (d) is preferably performed using ICP generated from at least one selected from the group consisting of N2, Ar, Cl2, BCl3, H2, and O2. The step (d) is preferably performed using ICP in a chamber having a pressure of 5-10 mTorr with a gas flow rate of 10-30 sccm, a source power of 200-800 W, and a chuck power of 50-100 W for 1-3 minutes.
The material used to form the gate electrodes in the step (c) and the material used to form the ohmic electrodes in the step (e) are deposited on the substrate by electron beam deposition or thermal deposition. The gate electrodes are formed of at least one selected from the group consisting of Pt, Pd, Ni, and Au. The ohmic electrodes are formed of a Ti/Al layer or a Ti/Al/Ni/Au layer.
Preferably, the substrate is a sapphire substrate or a silicon carbide substrate.